TRICONEX DO3401 数字输出模块 英维思卡件

TRICONEX DO3401 数字输出模块 英维思卡件

TRICONEX DO3401 数字输出模块 英维思卡件

ENDIAN转换-数据通道转向can在控制寄存器中配置，以允许不同的通信架构。字节交换，字交换和字节-字交换选项可用。防止数据丢失-数据节点从光纤电缆接收到错误检查并放入接收FIFO。

仲裁与然后从PCI总线进行访问，数据被写入节点的RAM和节点的传输FIFO。直接放置从PCI总线写入电路板的数据进入RAM和传输FIFO。传输中的数据FIFO由节点通过光缆传输到下一个节点。

要注意数据开始在FIFO中累积的唯一方法是以大于13.4 Mbyte/s的速率或冗余模式下为6.7 Mbyte/s。

因为数据可以从通过光纤和PCI总线，可能会超过这些速率。如果传输FIFO变为半满，则状态为一位寄存器已设置。这是对节点软件的指示对反射内存的后续写入应该是暂停，直到FIFO小于半满。如果半满忽略指示，传输FIFO，然后将确认对反射内存的写入停止*。不会丢失任何数据。

TRICONEX DO3401 数字输出模块 英维思卡件

ENDIAN conversion - Data channel steering can is configured in the control register to allow for different communication architectures. Byte exchange, word exchange, and byte-word exchange options are available. Prevent data loss - the data node receives an error check from the fiber optic cable and puts in the receive FIFO.

Mediated with and then accessed from the PCI bus, data is written to the node's RAM and the node's transmission FIFO. Place data written to the board from the PCI bus directly into RAM and transmit FIFO. The FIFO of data in transit is transmitted from the node to the next node via optical cable.

Note that the only way for data to start accumulating in the FIFO is at a rate greater than 13.4 Mbyte/s or 6.7 Mbyte/s in redundancy mode.

Because data can be passed from fiber to PCI bus, these rates may be exceeded. If the transfer FIFO becomes half full, the status is one bit register set. This is an indication to the node software that subsequent writes to reflected memory should be paused until the FIFO is less than half full. If half full ignores the indication, the FIFO is transmitted, and then the write to reflected memory is confirmed to stop *. No data will be lost.