MKD025B-144-KG1-UN REXROTH数字交流同步伺服电机 MKD系列

MKD025B-144-KG1-UN REXROTH数字交流同步伺服电机 MKD系列

MKD025B-144-KG1-UN定时器1 IRQ清除（T1IC）寄存器用于清除由定时器1引起的中断。写入该寄存器（位于BAR2中地址的偏移量0x30处）会导致定时器1的中断被清除。这也可以通过将“0”写入定时器控制状态寄存器（CSR1）的适当“定时器x引起的IRQ”字段。该寄存器仅写，写入的数据不相关。

读取此字段时，当前计数值被锁定并返回。有两种模式确定如何锁定计数，具体取决于WDT控制状态寄存器（CSR2）中的“读取锁存选择”位。参见CSR2有关这两种模式的更多信息/

定时器2 IRQ清除（T2IC）寄存器用于清除由定时器2引起的中断。写入该寄存器（位于BAR2中地址的偏移量0x34处）会导致定时器2的中断被清除。这也可以通过将“0”写入定时器控制状态寄存器（CSR1）的适当“定时器x引起的IRQ”字段。该寄存器仅写，写入的数据不相关。

The MKD025B-144-KG1-UN timer 1 IRQ Clear (T1IC) register is used to clear interrupts caused by timer 1. Writing to this register (at offset 0x30 of the address in BAR2) causes the interrupt of timer 1 to be cleared. This can also be done by writing "0" to the appropriate "IRQ caused by Timer x" field in the Timer Control Status Register (CSR1). The register is written only, and the data written is not relevant.

When this field is read, the current count value is locked and returned. There are two modes that determine how to lock the count, depending on the "Read latch Select" bit in the WDT Control status Register (CSR2). See CSR2 for more information on these two modes /

The timer 2 IRQ Clear (T2IC) register is used to clear interrupts caused by timer 2. Writing to this register (at offset 0x34 of the address in BAR2) causes the interrupt of timer 2 to be cleared. This can also be done by writing "0" to the appropriate "IRQ caused by Timer x" field in the Timer Control Status Register (CSR1). The register is written only, and the data written is not relevant.