HIMA X-SB01 985210207 模拟量调节器 EABT3 B9302 997009302

HIMA X-SB01 985210207 模拟量调节器 EABT3 B9302 997009302

DSP上电后首先进行引导程序的自加载，等待FPGA发送请求，在收到FPGA的请求后，DSP建立EDMA通道从FPGA获取视频数据，存满一帧后，开始对视频图像进行JPEG压缩处理，压缩处理后的视频图像信息经过FIFO缓存后，在 FPGA的控制下写入USB接口控制器的数据缓存区，等待PC机的读数请求，USB接口控制器在收到PC机的读数请求后将数据写入PDIUSBD12的端口1，以便PC机下一步读取数据。

　　2系统软件总体设计

系统的软件设计根据硬件结构的总体划分，也可以分为两大部分来描述。整个系统的运行如图2所示，FPGA和DSP各自的程序独立运行，通过中断信号完成数据的实时交互。FPGA向DSP方向的指令是通过FPGA发送一个EDMA请求，DSP通过响应EDMA请求，建立EDMA通道，开始从FIFO中进行预处理后数据的读取，DSP向FPGA传输数据时，通过向FPGA发送一个中断信号，让其从FIFO中把压缩后的图像数据读出来。

After powering on the DSP, the bootstrap program is self-loaded first and waits for the request from FPGA. After receiving the request from FPGA, the DSP establishes an EDMA channel to obtain video data from FPGA. After storing a full frame, the video image is compressed by JPEG and the compressed video image information is cached by FIFO. Under the control of FPGA, the data cache of the USB interface controller is written, waiting for the reading request of the PC, and the USB interface controller writes the data to port 1 of PDIUSBD12 after receiving the reading request of the PC, so that the PC can read the data in the next step.

2 Overall design of system software

The software design of the system can also be divided into two parts according to the overall division of the hardware structure. The operation of the whole system is shown in Figure 2. The programs of FPGA and DSP run independently and complete real-time data interaction through interrupt signals. The instruction from FPGA to DSP is to send an EDMA request through FPGA, and the DSP establishes an EDMA channel in response to the EDMA request and starts to read the pre-processed data from the FIFO. When the DSP transmits data to the FPGA, it sends an interrupt signal to the FPGA. Let it read the compressed image data out of the FIFO.