IP-QUADRATURE欧美备件 CPU模块 PLC控制器

IP-QUADRATURE欧美备件 CPU模块 PLC控制器

IP-QUADRATURE欧美备件 CPU模块 PLC控制器

IP-Quadrature计数器是用LS7166集成电路实现的。每个通道有一个IC；每个IP-Quadrature LS7166个IC。LS7166集成电路包含以下内部组件：

•24位计数器

•24位预设/比较寄存器

•24位输出锁存器

•24位比较器

•6位控制寄存器

•6位输入控制寄存器

•6位输出控制寄存器

•2位正交寄存器

•输入逻辑

•输出逻辑

每个通道可以被编程为使用X和Y输入以正交模式计数。或者，每个通道可以作为通用计数器操作，其中X和Y输入作为向上计数和向下计数脉冲输入，或作为计数输入和方向输入分别地对于中断，倒计数通常是首选，因为下溢（“借”）可能被编程为引起中断。在Match上也可能产生中断。这个预设/比较寄存器可以编程为任何值，包括$FFFFFF或$000000（至模拟“溢出”时的中断）。下溢和上溢都有专用的触发器，可以通过读取计数器的控制寄存器来读取。计数器寄存器和触发器被访问为LS7166计数器IC中的寄存器。

IP-QUADRATURE欧美备件 CPU模块 PLC控制器

The IP-Quadrature counter is implemented with the LS7166 integrated circuit. Each channel has one IC; Each IP-Quadrature LS7166 ics. The LS7166 integrated circuit consists of the following internal components:

• 24-bit counter

• 24-bit default/compare register

• 24-bit output latch

• 24-bit comparator

• 6-bit control register

• 6-bit input control register

• 6-bit output control register

• 2-bit orthogonal register

• Input logic

• Output logic

Each channel can be programmed to count in orthogonal mode using X and Y inputs. Alternatively, each channel can be operated as a universal counter, where the X and Y inputs are input as count up and count down pulses, or as count input and direction input, respectively, for interrupts, with backward counting often preferred because underflows (" borrows ") may be programmed to cause interrupts. Interrupts may also occur on Match. This default/comparison register can be programmed to any value, including $FFFFFF or $000000 (to simulate an "overflow" interrupt). Both underflows and overflows have dedicated triggers that can be read by reading the counter's control register. The counter registers and triggers are accessed as registers in the LS7166 counter IC.