METSO美卓 数字输出模块卡件 IOP331

METSO美卓 数字输出模块卡件 IOP331

METSO  IOP331每个计算元件都包含一个用于存储lut的二维存储器阵列、一个用于对子功能进行排序评估的小型控制器以及一组用于保存各个分区的中间输出的临时寄存器。每个计算模块内部的快速本地路由框架为LUT访问生成地址。

可以使用类似FPGA的可编程互连架构在空间上连接多个这样的计算元件，以实现大功能的映射。计算元件内部的本地时间复用执行可以大大减少对可编程互连的需求，从而导致能量延迟产品的巨大改进以及跨技术代的更好的性能可扩展性。

每个计算元件内部的存储器阵列可以通过以下方式实现相联存储器(CAM)大幅降低某些应用程序的内存需求。

METSO IOP331 Each computing element contains a two-dimensional memory array for storing the lut, a small controller for sorting evaluation of the sub-functions, and a set of temporary registers for holding the intermediate output of the individual partitions. A fast local routing framework inside each compute module generates addresses for LUT access.

Multiple such computing elements can be spatially connected using FPGA-like programmable interconnect architectures to enable mapping of large functions. Local time multiplexing execution within computing elements can significantly reduce the need for programmable interconnections, leading to huge improvements in energy delay products and better performance scalability across technology generations.

The memory array inside each computing element can be implemented in the following way associative memory (CAM) can significantly reduce memory requirements for some applications.