1756-IF16H 处理器 以太网模块 通讯模块

1756-IF16H 处理器 以太网模块 通讯模块

1756-IF16H 处理器 以太网模块 通讯模块

Allen-Bradley 1756-IF16H是1756 ControlLogix可编程逻辑控制器自动化(PAC)的模拟输入模块。它支持通过硬连线和高速可寻址远程传感器(HART)通信协议集成0-20 mA或4-20 mA输入信号。该模块每通道提供十六(16)个差分电流信号和一(1)个HART调制解调器。

1756-IF16H集成了采用逐次逼近法的模数转换器(ADC)。模拟转换分辨率范围为16-21位，允许显示更多的测量点。转换后的信号以整数模式保存(左对齐，2 s补码)IEEE 32位浮点数。

1756-IF16H的校准精度优于所有过滤器量程的0.13%，而模块误差为量程的0.3%。模块的输入扫描时间为11…328 ms，取决于滤波器，而如果所有通道都启用了HART，则模块HART扫描时间估计为1 s。

1756-IF16H 处理器 以太网模块 通讯模块

Allen-Bradley 1756-IF16H is an analog input module for the 1756 ControlLogix Programmable Logic Controller Automation (PAC). It supports the integration of 0-20 mA or 4-20 mA input signals via hardwired and high-speed addressable Remote Sensor (HART) communication protocols. The module provides sixteen (16) differential current signals and one (1) HART modem per channel.

The 1756-IF16H incorporates an analog-to-digital converter (ADC) using the successive approximation method. The analog conversion resolution ranges from 16-21 bits, allowing more measurement points to be displayed. The converted signal is saved in integer mode (left-justified, 2 s complement) as an IEEE 32-bit floating point number.

The calibration accuracy of the 1756-IF16H is better than 0.13% of all filter ranges, while the module error is 0.3% of the range. The input scan time of the module is 11... 328 ms, depending on the filter, while the module HART scan time is estimated to be 1 s if all channels are HART-enabled.