BENTLY 125388-01H全新到货PLC自动化备件

BENTLY 125388-01H全新到货PLC自动化备件

BENTLY 125388-01H全新到货PLC自动化备件

MB86S02视频图像传感器在FPGA的控制下进行视频图像信息的采集，在收到PC机的采集命令后MB86S02开始视频信号的采集 FPGA作为系统的核心控制单元不仅负责视频图像的采集，而且负责视频图像信息的预处理和系统各单元模块之间的数据交互。

针对视频图像数据量大的特点，为了保证系统的实时性要求，系统采用大容量的片外SDRAMR对采集到的视频图像信息进行缓存，SDRAM控制器由FPGA实现，视频图像信息经过 SDRAM缓存后首先要由FPGA对其进行滤波处理，以消除图像信息中的噪声干扰，本系统中采用中值滤波的方式对采集到的视频信息进行处理，滤波后的数据通过FPGA内部FIFO进入DSP进行下一步的压缩处理。

DSP上电后首先进行引导程序的自加载，等待FPGA发送请求，在收到FPGA的请求后，DSP建立EDMA通道从FPGA获取视频数据，存满一帧后，开始对视频图像进行JPEG压缩处理，压缩处理后的视频图像信息经过FIFO缓存后，在 FPGA的控制下写入USB接口控制器的数据缓存区，等待PC机的读数请求，USB接口控制器在收到PC机的读数请求后将数据写入PDIUSBD12的端口1，以便PC机下一步读取数据。

BENTLY 125388-01H全新到货PLC自动化备件

MB86S02 video image sensor collects video image information under the control of FPGA. MB86S02 starts video signal acquisition after receiving the acquisition command from PC. FPGA, as the core control unit of the system, is not only responsible for video image acquisition. It is also responsible for the pre-processing of video image information and the data interaction between each unit module of the system.

In view of the large amount of video image data, in order to ensure the real-time requirements of the system, the system adopts large-capacity off-chip SDRAMR to cache the collected video image information. The SDRAM controller is implemented by FPGA, and the video image information must be filtered by FPGA after being cached by SDRAM. In order to eliminate the noise interference in the image information, the system uses the median filter to process the collected video information, and the filtered data enters the DSP through the FPGA internal FIFO for the next step of compression processing.

After powering on the DSP, the bootstrap program is self-loaded first and waits for the request from FPGA. After receiving the request from FPGA, the DSP establishes an EDMA channel to obtain video data from FPGA. After storing a full frame, the video image is compressed by JPEG and the compressed video image information is cached by FIFO. Under the control of FPGA, the data cache of the USB interface controller is written, waiting for the reading request of the PC, and the USB interface controller writes the data to port 1 of PDIUSBD12 after receiving the reading request of the PC, so that the PC can read the data in the next step.